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| cots pem ssram as5sp256k36 as5sp256k36 rev. 2.2 10/13 micross components reserves the right to change products or speci cations without notice. 1 plastic encapsulated microcircuit 9.0mb, 256k x 36, synchronous sram pipeline burst, single cycle deselect features ? synchronous operation in relation to the input clock ? 2 stage registers resulting in pipeline operation ? on chip address counter (base +3) for burst operations ? self-timed write cycles ? on-chip address and control registers ? byte write support ? global write support ? on-chip low power mode [powerdown] via zz pin ? interleaved or linear burst support via mode pin ? three chip enables for ease of depth expansion without data contention. ? two cycle load, single cycle deselect ? asynchronous output enable (oe\) ? three pin burst control (adsp\, adsc\, adv\) ? 3.3v core power supply ? 3.3v/2.5v io power supply ? jedec standard 100 pin tqfp package, ? available in industrial , enhanced , and mil-temperature operating ranges ? rohs compliant options available paramete r symbol 200mhz 166mhz 133mhz units cycle time tcyc 5.0 6.0 7.5 ns clock access time tcd 3.0 3.5 4.0 ns output enable access time toe 3.0 3.5 4.0 ns fast access times block diagram general description the as5sp256k36 is a 9.0mb high performance synchronous pipeline burst sram, available in multiple temperature screening levels, fabricated using high performance cmos technology and is organized as a 256k x 36. it integrates address and control registers, a two (2) bit burst address counter supporting four (4) double-word transfers. writes are internally self-timed and synchronous to the rising edge of clock. the as5sp256k36 includes advanced control options including global write, byte write as well as an asynchronous output enable. burst cycle controls are handled by three (3) input pins, adv\, adsp\ and adsc\. burst operation can be initiated with either the address strobe processor (adsp\) or address strobe controller (adsc\) inputs. subsequent burst addresses are generated internally in the system?s burst sequence control block and are controlled by address advance (adv\) control input. control block burst cntl. address registers row decode column decode memory array x36 sbp i/o gating and control output register input register clk ce1\ ce2 ce3\ bwe\ bwx\ gw\ adv \ adsc\ adsp\ mode a0-ax dqx, dqp output driver ? synchronous pipeline burst ? two (2) cycle load ? one (1) cycle de-select ? one (1) cycle latency on mode change oe\ zz dqpc dqc dqc dqc dqc dqc dqc dqd dqd dqd dqd dqd dqd dqd dqd dqc dqc dqb dqb dqb dqb dqb dqb dqb dqb dqa dqa dqa dqa dqa dqa dqa dqa dqp dqp vdd vddq vdd vdd vssq vssq vssq vssq vss vdd nc vddq vddq vddq vddq vssq vssq vssq vssq ssram [spb] 1 2 3 4 5 6 7 8 9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 zz 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 nc nc vdd vss 22 21 20 19 18 17 16 15 14 13 12 10 11 a a adv\ adsp\ oe\ bwe\ gw\ clk vss vdd ce3\ bwa\ bwb\ bwc\ bwd\ ce2 ce1\ adsc\ a a mode a a a a a1 a0 nc* nc* vss vdd nc* a a a a a a a dqpd a
cots pem ssram as5sp256k36 as5sp256k36 rev. 2.2 10/13 micross components reserves the right to change products or speci cations without notice. 2 pin description / assignment table signal nam e symbol type pin descriptio n clock clk input 89 this input captures all synchronous inputs to the device as well as synchronizes the burst control functions. address a0, a1 input 37, 36 low order, synchronous address inputs and burst counter address inputs address a input(s) 35, 34, 33, 32, 31, 100, synchronous address inputs 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 4 3 chip enable ce1\, ce3\ input 98, 92 active low true chip enables chip enabl e ce2 inpu t 97 a ctive high true chip enabl e global write enable gw\ input 88 active low true global write enable. write to all bits byte enables bwa\, bwb\, input 93, 94, 95, 96 active low true byte write enables. write to byte segments bwc\, bwd\ byte write enable bwe\ input 87 active low true byte write function enable output enable oe\ input 86 active low true asynchronous output enable address strobe controller adsc\ input 85 address strobe from controller. when asserted low, address is captured in the address registers and a0-a1 are loaded into the bu r when adsp\ and adsc are both asserted, only adsp is recognized address strobe from processor adsp\ input 84 address strobe from processor. when asserted low, address is captured in the address registers, a0-a1 is registered in the burst counter. when both adsp\ and adsc\ or both asserted, only adsp\ is recognized. adsp\ is ignored when ce1\ is high address advance adv\ input 83 advance input address. when asserted low, address in burst counter is incremented. power-down zz input 64 asynchronous, non-time critical power-down input control. places the chip into an ultra low power mode, with data preserved. data parity input/outputs dqpa, dqpb input/ 51, 80, 1, 30 bidirectional i/o parity lines. as inputs they reach the memory dqpc, dqpd output array via data register, that is triggered on the rising edge of clock. as an output, the line delivers the valid data stored in the array via an output register and output driver. the data delievered is from the previous clock period of the read cycle. data input/output s dqa, dqb, dq c input / 52, 53, 56, 57, 58, 59 , bidirectional i/o parity lines. as inputs they reach the memo dqd output 62, 63, 68, 69, 72, 73, array via data register, that is triggered on the 74, 75, 78, 79, 2, 3, 6, rising edge of clock. as an output, the line delivers the valid data 7, 8, 9, 12, 13, 18, 19, stored in the array via an output register and output driver. the data 22, 23, 24, 25, 28, 29 delievered is from the previous clock period of the read cycle. burst mode mode input 31 interleaved or linear burst mode control power supply [core] vdd supply 91, 15, 41, 65 core power supply ground [core ] v ss suppl y 90, 17, 40, 6 7 core power supply groun d power supply i/o vddq supply 4, 11, 20, 27, 54, 61, isolated input/output buffer supply 70, 77 i/o ground vssq supply 5, 10, 21, 26, 55, 60, isolated input/output buffer ground 71, 76 no connection(s) nc na 14, 16, 38, 39, 65 no connections to internal silicon cots pem ssram as5sp256k36 as5sp256k36 rev. 2.2 10/13 micross components reserves the right to change products or speci cations without notice. 3 logic block diagram address register adv clk burst counter and logic clr q1 q0 adsp adsc mode bwe gw ce 1 ce 2 ce 3 oe enable register output registers sense amps output buffers e pipelined enable input registers a 0, a1, a bw b bw c bw d bw a memory array dqs dqp a dqp b dqp c dqp d sleep control zz a [1:0] 2 dq a, dqp a byte write register dq b, dqp b byte write register dq c, dqp c byte write register dq d, dqp d byte write register dq a, dqp a byte write driver dq b, dqp b byte write driver dq c, dqp c byte write driver dq d ,dqp d byte write driver cots pem ssram as5sp256k36 as5sp256k36 rev. 2.2 10/13 micross components reserves the right to change products or speci cations without notice. 4 micross components as5sp256k36 synchronous sram is manufactured to support today?s high performance platforms utilizing the industries leading processor elements including those of intel and motorola. the as5sp256k36 supports synchronous sram read and write operations as well as synchronous burst read/write operations. all inputs with the exception of oe\, mode and zz are synchronous in nature and sampled and registered on the rising edge of the devices input clock (clk). the type, start and the duration of burst mode operations is controlled by mode, adsc\, adsp\ and adv\ as well as the chip enable pins ce1\, ce2, and ce3\. all synchronous accesses including the burst accesses are enabled via the use of the multiple enable pins and wait state insertion is supported and controlled via the use of the advance control (adv\). the as5sp256k36 supports both interleaved as well as linear burst modes therefore making it an architectural t for either the intel or motorola cisc processor elements available on the market today. the as5sp256k36 supports byte write operations and enters this functional mode with the byte write enable (bwe\) and the byte write select pin(s) (bwa\, bwb\, bwc\, bwd\). global writes are supported via the global write enable (gw\) and global write enable will override the byte write inputs and will perform a write to all data i/os. the as5sp256k36 provides ease of producing very dense arrays via the multiple chip enable input pins and tri-state outputs. single cycle access operations a single read operation is initiated when all of the following conditions are satis ed at the time of clock (clk) high: [1] adsp\ or adsc\ is asserted low, [2] chip enables are all asserted active, and [3] the write signals (gw\, bwe\) are in their false state (high). adsp\ is ignored if ce1\ is high. the address presented to the address inputs is stored within the address registers and address counter/advancement logic and then passed or presented to the array core. the corresponding data of the addressed location is propagated to the output registers and passed to the data bus on the next rising clock via the output buffers. the time at which the data is presented to the data bus is as speci ed by either the clock to data valid speci cation or the output enable to data valid spec for the device speed grade chosen. the only exception occurs when the device is recovering from a deselected to select state where its outputs are tristated in the rst machine cycle and controlled by its output enable (oe\) on following cycle. consecutive single cycle reads are supported. once the read operation has been completed and deselected by use of the chip enable(s) and either adsp\ or adsc\, its outputs will tri-state immediately. a single adsp\ controlled write operation is initiated when both of the following conditions are satis ed at the time of clock (clk) high: [1] adsp\ is asserted low, and [2] chip enable(s) are asserted active. the address presented to the address bus is registered and loaded on clk high, then presented to the core array. the write controls global write, and byte write enable (gw\, bwe\) as well as the individual byte writes (bwa\, bwb\, bwc\, and bwd\) and adv\ are ignored on the rst machine cycle. adsp\ triggered write accesses require two (2) machine cycles to complete. if global write is asserted low on the second clock (clk) rise, the data presented to the array via the data bus will be written into the array at the corresponding address location speci ed by the address bus. if gw\ is high (inactive) then bwe\ and one or more of the byte write controls (bwa\, bwb\, bwc\ and bwd\) controls the write operation. all writes that are initiated in this device are internally self timed. a single adsc\ controlled write operation is initiated when the following conditions are satis ed: [1] adsc\ is asserted low, [2] adsp\ is de-asserted (high), [3] chip enable(s) are asserted (true or active), and [4] the appropriate combination of the write inputs (gw\, bwe\, bwx\) are asserted (active). thus completing the write to the desired byte(s) or the complete data-path. adsc\ triggered write accesses require a single clock (clk) machine cycle to complete. the address presented to the input address bus pins at time of clock high will be the location that the write occurs. the adv\ pin is ignored during this cycle, and the data written to the array will either be a byte write or a global write depending on the use of the write control functions gw\ and bwe\ as well as the individual byte contols (bwx\). deep power-down mode (sleep) the as5sp256k36 has a deep power-down mode and is controlled by the zz pin. the zz pin is an asynchronous input and asserting this pin places the ssram in a deep power- down mode (sleep). while in this mode, data integrity is guaranteed. for the device to be placed successfully into this operational mode the device must be deselected and the chip enables, adsp\ and adsc\ remain inactive for the duration of tzzrec after the zz input returns low. use of this deep power-down mode conserves power and is very useful in multiple memory page designs where the mode recovery time can be hidden. functional description cots pem ssram as5sp256k36 as5sp256k36 rev. 2.2 10/13 micross components reserves the right to change products or speci cations without notice. 5 synchronous truth tables burst sequence tables interleaved burs t burst control state case 1 case 2 case 3 case 4 pin [mode] high a1 a0 a1 a0 a1 a0 a1 a first address 0001101 0100111 1011000 fourth address 1 1 1 0 0 1 0 linear burst burst control state case 1 case 2 case 3 case 4 pin [mode] low a1 a 0 a 1 a 0 a 1a0 a 1 a first address 0001101 0110110 1011000 fourth address 1100011 capacitance paramete r symbol max. units input capacitance ci 6pf input/output capacitance cio 8pf clock input capacitance ccl k 6pf write table gw \ bw \ bwa \ bwb \ bwc \ bwd \ operation hhxxxx read hlhhhh read h l l h h h write byte [a] h l h l h h write byte [b] h l h h l l write byte [c], [d] h l l l l l write all bytes lxxxxx write all bytes absolute maximum ratings absolute maximum ratings parameter symbol min. max. units voltage on vdd pin vdd -0.3 4.6 v voltage on vddq pins v ddq vdd v voltage on input pins v in -0.3 vdd+0.3 v voltage on i/o pins v io -0.3 vddq+0.3 v power dissipation pd 1.6 w storage temperature tstg -65 150 r c operating temperatures / it -40 85 r c [screening levels] / et -40 105 r c / xt -55 125 r c *stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this speci cation is not implied. exposure to absolute maximum conditions for any duration or segment of time may affect device reliability. asynchronous truth table operation zz oe\ i/o status power-down (sleep) h x high-z read l l dq l h high-z write l x din, high-z de-selected l x high-z ac test loads r= 1538 ohm@2.5v r= 351 ohm@3.3v 3.3/2.5v output diagram [b] 5 pf r= 317 ohm@3.3v r= 1667 ohm@2.5v output zo=50 ohm 30 pf rt = 50 ohm vt= termination voltage rt= termination resistor vt= 1.50v for 3.3v vddq vt= 1.25v for 2.5v vddq diagram [a] ce1\ ce2 ce3\ adsp \ adsc \ adv \ wt / rd cl k address accesse d operatio n h x x x l x x na not selected l l x l x x x na not selected l x h l x x x na not selected l l x h l x x na not selected l x h h l x x na not selected l h l l x x x external address begin burst, read l h l h l x wt external address begin burst, write l h l h l x rd external address begin burst, read x x x h h l rd next address continue burst, read h x x x h l rd next address continue burst, read x x x h h l wt next address continue burst, write h x x x h l wt next address continue burst, write x x x h h h rd current address suspend burst, read h x x x h h rd current address suspend burst, read x x x h h h wt current addres s suspend burst, writ e h x x x h h wt current address suspend burst, write notes: 1. x = don?t care 2. wt= write operation in write table, rd= read operation in write table cots pem ssram as5sp256k36 as5sp256k36 rev. 2.2 10/13 micross components reserves the right to change products or speci cations without notice. 6 dc electrical characteristics (vdd=3.3v -5%/+10%), ta= min. and max temperatures of screening level chosen) thermal resistance parameter description test conditions dq package dqc package unit : ja thermal resistance (junction to ambient) 29.41 30.2 o c/w : jc thermal resistance (junction to case) 6.13 6.5 o c/w test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51 notes: [1] all voltages referenced to vss (logic ground) [2] overshoot: vih < +4.6v for t cots pem ssram as5sp256k36 as5sp256k36 rev. 2.2 10/13 micross components reserves the right to change products or speci cations without notice. 7 ac switching characteristics (vdd=vddq=3.3v -5%/+10%,) ta= min. and max temperatures of screening level chosen) -30 [200mhz] -35 [166mhz] -40 [133mhz] parameter symbol min. max. min. max. min. max. units notes clock (clk) cycle time tcyc 5.00 - 6.00 - 7.50 - ns clock (clk) high time tch 2.00 - 2.20 - 2.50 - ns 1 clock (clk) low time tcl 2.00 - 2.20 - 2.50 - ns 1 clock access time tcd 3.00 3.50 4.00 ns 2 clock (clk) high to output low-z tclz 1.25 - 1.25 - 1.25 - ns 2,3,4,5 clock high to output high-z tchz 1.25 3.00 1.25 3.50 1.25 3.50 ns 2,3,4,5 output enable to data valid toe - 3.00 - 3.50 - 4.00 ns 6 output hold from clock high toh 1.25 - 1.25 - 1.25 - ns output enable low to output low-z toelz 0.00 - 0.00 - 0.00 - ns 2,3,4,5 output enable high to output high-z toehz - 3.00 - 3.50 - 3.50 ns 2,3,4,5 address set-up to clk high tas 1.40 1.50 1.50 ns 7,8 address hold from clk high tah 0.40 0.50 0.50 ns 7,8 address status set-up to clk high tass 1.40 1.50 1.50 ns 7,8 address status hold from clk high tash 0.40 0.50 0.50 ns 7,8 address advance set-up to clk high tadvs 1.40 1.50 1.50 ns 7,8 address advance hold from clk high tadvh 0.40 0.50 0.50 ns 7,8 chip enable set-up to clk high (cex\, ce2) tces 1.40 1.50 1.50 ns 7,8 chip enable hold from clk high (cex\, ce2) tceh 0.40 0.50 0.50 ns 7,8 data set-up to clk high tds 1.40 1.50 1.50 ns 7,8 data hold from clk high tdh 0.40 0.50 0.50 ns 7,8 write set-up to clk high (gw\, bwe\, bwx\) twes 1.40 1.50 1.50 ns 7,8 write hold from clk high (gw\, bwe\, bwx\) tweh 0.40 0.50 0.50 ns 7,8 zz high to power down tpd 2 2 2 cycles zz low to power up tpu 2 2 2 cycles 1. measured as high when above vih and low when below vil 2. this parameter is measured with the output loading shown in ac test loads 3. this parameter is sampled 4. transition is measured +500mv from steady state voltage 5. critical specification(s) when design considerations are being reviewed/analyized for bus contentention 6. oe\ is a don't care when a byte or global write is sampled low 7. a read cycle is defined by byte or global writes sampled low and adsp\ is sampled high for the required set-up and hold times 8. this is a synchronous device. all addresses must meet the specified set-up and hold times for all rising edges of clk when e ither adsp\ or adsc\ is sampled low while the device is enabled. all other synchronous inputs must meet the set-up and hold times with stable logic levels for all rising edges of clock (clk) during device operation (enabled). chip enable (cex\, ce2) must b e valid at each rising edge of clock (clk) when either adsp\ or adsc\ is low to remain enabled. 9. this part has a voltage regulator internally; tpower is the time that the power needs to be supplied above vdd (minimum) initia lly before a read or write operation can be initiated. cots pem ssram as5sp256k36 as5sp256k36 rev. 2.2 10/13 micross components reserves the right to change products or speci cations without notice. 8 ac switching waveforms write cycle timing clk adsp\ adsc\ adv\ ax gw\ bwe\, bwx\ ce1\ ce2 ce3\ oe\ dqx,dqpx a1 a2 a3 w1 w2a w2b w2d w2c w3 don't care undefined single write burst write pipelined write tcyc tch tcl tash tass adsp\ ignored with ce1\ inactive tash tass tadvs tadvh adv\ must be inactive for adsp\ write tas tah twes tweh tweh twes tces tceh ce1\ masks adsp\ tds tdh cots pem ssram as5sp256k36 as5sp256k36 rev. 2.2 10/13 micross components reserves the right to change products or speci cations without notice. 9 ac switching waveforms read cycle timing clk adsp\ adsc\ adv\ ax gw\ bwe\, bwx\ ce1\ ce2 ce3\ oe\ dqx,dqpx a1 a2 a3 undefined don't care single read burst read pipelined read tcyc tass tash adsp\ ignored with ce1\ inactive tch tcl tadvs tadvh suspend burst adsc\ initiated read tas tah twes tweh tces tceh ce1\ masks adsp\ unselected with ce2 toe toehz tcd toh r1 r2a r2b r2c r2d r3a cots pem ssram as5sp256k36 as5sp256k36 rev. 2.2 10/13 micross components reserves the right to change products or speci cations without notice. 10 ac switching waveforms read / write cycle timing clk adsp\ adsc\ adv\ ax gw\ bwe\, bwx\ ce1\ ce2 ce3\ oe\ dqx,dqpx a1r a2w a3w a4r a5r a1o a2i a3i a4o a4o a4o a4o [a] [b] [c] [d] burst read pipelined read tcyc tch tcl tass tash tadvs tadvh tah tas twes tweh tces tceh tceh tces toe toehz toelz tcd toh undefined don't care cots pem ssram as5sp256k36 as5sp256k36 rev. 2.2 10/13 micross components reserves the right to change products or speci cations without notice. 11 power down (snooze mode) power down or snooze is a power conservation mode which when building large/very dense arrays, using multiple devices in a multi-banked or paged array, can greatly reduce the operating current requirements of your total memory array solution. the device is placed in this mode via the use of the zz pin, an asynchronous control pin which when asserted, places the array into the lower power or power down mode. awakening the array or leaving the power down (snooze) mode is done so by de-asserting the zz pin . while in the power down or snooze mode, data integrity is guaranteed. accesses pending when the device entered the mode are not considered valid nor is the completion of the operation guaranteed. the device must be de-selected prior to entering the power down mode, all chip enables, adsp\ and adsc\ must remain inactive for the duration of zz recovery time (tzzrec). parameter symbol test condito n min. max. unit s power down (snooze) mode iddzz zz >/- vdd - 0.2v 75 ma zz active (signal high) to power down tzzs zz >/- vdd - 0.2v 2 tcyc ns zz inactive (signal low) to power up tzz r zz cots pem ssram as5sp256k36 as5sp256k36 rev. 2.2 10/13 micross components reserves the right to change products or speci cations without notice. 12 100-pin tqfp (package designator dq) mechanical definition cots pem ssram as5sp256k36 as5sp256k36 rev. 2.2 10/13 micross components reserves the right to change products or speci cations without notice. 13 ordering information *available processes it = industrial temperature range -40 o c to +85 o c et = enhanced temperature range -40 o c to +105 o c xt = military temperature range -55 o c to +125 o c tqfp tcd clock (ns) (mhz) as5sp256k36dq-30/i t 256kx36, 3.3vcore/3.3,2.5vio 3.0 200 * as5sp256k36dq-35/i t 256kx36, 3.3vcore/3.3,2.5vio 3.5 166 as5sp256k36dq-40/i t 256kx36, 3.3vcore/3.3,2.5vio 4.0 133 as5sp256k36dq-30/e t 256kx36, 3.3vcore/3.3,2.5vio 3.0 200 as5sp256k36dq-35/e t 256kx36, 3.3vcore/3.3,2.5vio 3.5 166 as5sp256k36dq-40/e t 256kx36, 3.3vcore/3.3,2.5vio 4.0 133 as5sp256k36dq-35/x t 256kx36, 3.3vcore/3.3,2.5vio 3.5 166 as5sp256k36dq-40/x t 256kx36, 3.3vcore/3.3,2.5vio 4.0 133 device number configuration cots pem ssram as5sp256k36 as5sp256k36 rev. 2.2 10/13 micross components reserves the right to change products or speci cations without notice. 14 document title 256k x 36, synchronous sram pipeline burst, single cycle deselect revision history rev # history release date status 1.6 updated assignment table to indicate june 2009 release adv\ low 1.7 changed all references to adv\ june 2009 release 1.8 updated dc chart july 2009 release 1.9 added micross information january 2010 release 2.0 added copper lead frame and rohs may 2011 release compliant options, updated iddzz from 60ma to 75ma, updated logic block diagram on page 2. deleted i sb3 & i sb4 specs. changed: from to i dd max (-30) 220ma 275ma (-35) 180ma 250ma (-40) 140ma 225ma i sb1 max (-30) 120ma 150ma (-35) 110ma 140ma (-40) 100ma 130ma i sb2 max 40ma 110ma c i &c clk 5pf 6pf c io 5pf 8pf j a 35 o c/w 29.41 o c/w j c 9 o c/w 6.13 o c/w 2.1 added thermal resistance for dqc september 2011 release package, page 6. 2.2 removed cu-lead frame option october 2013 release |
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